FPGA implementation of a novel DCT architecture reducing constant cosine terms

Abstract

This paper presents a new scalable architecture for Discrete Cosine Transform (DCT). In contrast to the conventional DCT architecture, the proposed architecture reduces the number of constant cosine terms using the matrix transposition and symmetry property. This in turn, considerably reduces the computation time. The architecture is scalable and it can be extended to support any transform length. The architecture was validated on Xilinx Vertex-4 FPGA.