FPGA implementation of a new interval type-2 Beta neuro-fuzzy system with on-chip learning for image denoising application

Abstract

Hardware implementation of conventional interval type-2 neuro-fuzzy systems with on-chip learning is essential for real time applications. However, existing implementations are resource consuming due to the complexity of their architectures and the use of iterative procedure for system output estimation. To overcome this problem, we propose a new interval type-2 neuro-fuzzy architecture. Accordingly, the number of layers is reduced owing to using Beta membership functions. Moreover, a simplified output computing operation is applied. For implementing Beta functions, an accurate and compact Centered Recursive Interpolation (CRI) method is used. For on-chip learning system, a new on-line incremental learning algorithm with gradient descent technique is applied to adjust its parameters. Furthermore, a synthesis of the corresponding design on a Field Programmable Gate Array (FPGA) platform is achieved in image denoising application. Performances comparison with the existing implementations shows the effectiveness of our chip in terms of resource requirements, speed and denoising performances.