FPGA Implementation of a New DTC Strategy Dedicated to Delta Inverter-Fed BLDC Motor Drives

Abstract

This paper presents the field programmable gate array (FPGA) implementation of an ameliorated direct torque control strategy (DTC-2) for a brushless DC motor (BLDCM) fed by a reduced delta inverter, called also three-switch three-phase inverter (TSTPI). In this work, a DTC-fed BLDCM drive is treated by considering two strategies. The first strategy (DTC-1) emulates the operation of the conventional inverter where the original DTC control is applied. Based on the DTC-1 strategy, high ripples of the electromagnetic torque are registered during the sector-to-sector commutations. These ripples are due to the application of unbalanced voltage vectors. To overcome these drawbacks, an ameliorated strategy (DTC-2) is proposed. This second strategy consists in decreasing the sudden transition between lower and upper voltage vectors by the synthesis of an appropriate vector selection table. The particularity of this table is based on the application of switching voltage vectors during a defined period of each commutation sector operation. In this paper, the two DTC strategies are developed, simulated and checked under the Xilinx system generator environment. Both strategies are translated into a hardware implementation using an FPGA device (Virtex 5). The hardware co-simulation results clearly validate the performances of the association BLDCM-TSTPI under the second ameliorated control strategy DTC-2.