FPGA Implementation of A∗ Algorithm for Real-Time Path Planning

Xi Jin,Yuzhi Zhou,Tianqi Wang

doi:10.1155/2020/8896386

Abstract

The traditional A∗ algorithm is time-consuming due to a large number of iteration operations to calculate the evaluation function and sort the OPEN list. To achieve real-time path-planning performance, a hardware accelerator’s architecture called A∗ accelerator has been designed and implemented in field programmable gate array (FPGA). The specially designed 8-port cache and OPEN list array are introduced to tackle the calculation bottleneck. The system-on-a-chip (SOC) design is implemented in Xilinx Kintex-7 FPGA to evaluate A∗ accelerator. Experiments show that the hardware accelerator achieves 37–75 times performance enhancement relative to software implementation. It is suitable for real-time path-planning applications.

Highlights

Path planning on grid maps is still an important problem in many modern domains, such as robotics [1], vessel navigation [2], and commercial computer games [3]
This paper introduces a hardware framework to accelerate the performance of the A∗ algorithm by parallelizing the iteration operations. e scientific code could benefit from executing on accelerators like field programmable gate arrays (FPGAs) [8]. e calculation bottleneck mainly focuses on two parts, calculating and sorting the evaluation value of each node. e evaluation value is used to determine the searching steps
We demonstrate the design’s implementation to maps with 256 × 256 resolution, and it is scalable to bigger maps. en the hardware system-on-a-chip (SOC) will be introduced briefly to show the implementation process in field programmable gate array (FPGA)

Summary

Introduction

Path planning on grid maps is still an important problem in many modern domains, such as robotics [1], vessel navigation [2], and commercial computer games [3]. It generates the global optimal paths dynamically and can theoretically guarantee the convergence of the global optimal solution [5] Such characteristic makes it suitable for dynamically changed maps such as real-time path planning in robotics or RTS games. This paper introduces a hardware framework to accelerate the performance of the A∗ algorithm by parallelizing the iteration operations. Results show that 37–75 times performance enhancement could be achieved with the accelerator’s clock frequency at 100 MHz. is research makes the following contributions: International Journal of Reconfigurable Computing (1) e exploration of the way to accelerate the performance of the A∗ algorithm by parallelizing the iteration operations. Experimental results show that parallelizing the iteration operations of A∗ algorithm can achieve massive performance enhancement, and the hardware design is suitable for applications with real-time performance requirements.

Related work

Algorithm

Evaluation engine

System Design

Experiments Results and Discussions

Design option

Optimization methods