FPGA implementation of a factorization processor for soft-decision reed-solomon decoding

Abstract

In this paper, we present a high-speed FPGA implementation for the factorization step of algebraic soft-decision Reed-Solomon (RS) decoding algorithms. The design is based on the root-order prediction architecture. Parallel processing is exploited to speed up the polynomial updating involved in the factorization. To resolve the data dependency issue in parallel polynomial updating, we propose an efficient coefficient storage and transfer scheme, which leads to smaller memory usage and low latency. Synthesis results show that the factorization processor for a (255, 239) RS code with maximum multiplicity four can achieve an average decoding speed of 226 Mbps on a Xilinx Virtex-II FPGA device when the frame error rate is less than 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">−2</sup> .