FPGA Implementation for Speed Controlling of 8/6 Switched Reluctance Motor using PI Controller

Abstract

This paper presents the field programmable gate array (FPGA) implementation for the speed controlling of 8/6 switched reluctance motor (SRM) using conventional proportional integral (PI) controller. PI controller is tuned by trial and error method such that the actual speed of motor follows reference speed under different loading conditions. The main focus of the paper is to construct and implement the commutation table for consecutive excitation of the successive phases of SRM. In order to implement it, an inductance profile of SRM is stored into the ROM indicating the direction of the rotor. Four hall sensors are used to obtain the pulses from the respective phases and compared with inductance profile to excite the appropriate phases. The entire algorithm is modeled using Xilinx tool box and wavect controller to integrate SRM with asymmetric converter. The developed Xilinx model is validated for load and no-load condition and the experimental results are presented.