FPGA Implementation for Skeletonization of 2-D Images

Abstract

The embedded multimedia devices which are designed to perform computationally intensive DSP applications such as Image Processing and a large range of multimedia tasks. For improving the performance of image processing systems, processing algorithms should be implemented in hardware platforms. For real time applications, reconfigurable hardware in the form of Field Programmable Gate Arrays (FPGAs) are used which are able to provide high performance with low latency. The inherent reprogram ability of FPGAs gives them the flexibility of software while retaining the performance advantages of an application specific solution. In real time applications as image sizes grow larger, only real-time hardware systems have to be used with less software. This paper proposes a fully pipelined architecture implementation of skeletonization algorithm for 2-D gray scale images. 3x3 windowing operator is used for analyzing the pixel values. The proposed architecture is tested for image size of 8x8, but the approach discussed can be used for images of any size, as long as the FPGA memory will hold it. The implementation was carried out on Xilinx Vertex 5 board.