FPGA Implementation for a Chaotic Digital Receiver Using Duffing Oscillators Array

Abstract

Chaotic signal is suitable for secure communication because of its concealment, unpredictability, high complexity and easy implementation. This paper aims for the complete FPGA implementation to enable hardware design of the chaotic digital receiver that using Duffing oscillator's array operating at the same frequency. Taking account the time-domain signal of chaotic Duffing oscillator has concealment and noise-like characteristics; it can be used to construct more secure communication information in signal modulation. During demodulation, we utilized the amplitude sensitivity of the signal and shielded its phase sensitivity by using Duffing oscillators array, so that it can demodulate binary chaotic signal with arbitrary phases. This paper analyzed the response of Duffing oscillator to chaotic signal. A Duffing oscillators array is used to receive chaotic digital signal and the fourth-order Runge-Kutta algorithm is introduced to solve the Duffing equation. Under the condition of conventional receiver, a Duffing oscillator optimization is added to improve the receiver's overall performance. Finally, a chaotic digital receiver of Duffing oscillator based on FPGA was completed, and the result, obtained using the ModelSim simulation platform and SignalTap II tool, indicates the correction of this receiver.