FPGA hardware-in-loop co-simulation for THIPWM controlled multilevel inverter

Abstract

In this paper, FPGA(Field Programmable Gate Array) hardware-in-loop co-simulation (Hardware co-simulation)is proposed for controller prototyping of Cascaded H-bridge multilevel inverter(CHBMLI). Third harmonics injected pulse width modulation(THIPWM) technique is used for controller prototyping. Mathematical analysis of THIPWM control is investigated for improved dc bus voltage utilization and extension of linearity range. Control model of THIPWM for five and seven level inverter incorporating Phase shifted and level shifted carrier signals are generated using Xilinx system generator(XSG) platform in Matlab/simulink. Real time Hardware co-simulation is performed by modelling CHBMLI system in Matlab/simulink and hardware co-simulation is performed using Zedboard Zynq development and evaluation FPGA kit.