FPGA hardware in the loop system for ERTMS-ETCS train equipment testing

Abstract

At the heart of the European Rail Train Management System (ERTMS) is the European Train Control System (ETCS). One major goal of the ERTMS-ETCS project is the standardization and unification of all train control and command systems in Europe. Hence, it is critical to have a reliable test bed for ease of validation and certification, enforcing the reliability of ERTMS-ETCS train equipment. In this context, we present a low-cost system comprised of several connected Heterogeneous System on Chip (HSoC) cards that are used for the purpose of certifying train equipment. The proposed system mimics real train behaviors in operation. Train behavior scenarios are controlled by a train motion simulator running on a host PC, and train behavior data is fed from our system to the train equipment undergoing testing. An intermediate extension is used to guarantee real-time data transmission since the simulator is not capable of doing so due to its high computation demands and communication latencies. In our intermediate extension, each HSoC card contains a NVIDIA Tegra 2 microprocessor chip, an Altera Cyclone II Field Programmable Gate Array (FPGA) chip and several custom Application Specific Integrated Circuit (ASIC) chips. Each card can be accessed by the simulator over a Gigabit Ethernet port, and all cards intercommunicate using a 1 Mbps back-plane serial bus. We show that by using simulations as a starting point, our system is able to generate authentic train control signals 20 times faster than the software simulator in real-time, presenting the train equipment with a real test case scenario accurately modelling train behavior over a track.1