FPGA hardware implementation of the LZMA compression algorithm

Abstract

Software-based LZMA( Lempel Ziv Markov-chain algorithm) nondestructive compression algorithm is very slow and consumes too much CPU( central processing unit) resources during the data compression process,as a result it can not meet the requirements of real-time systems. On the basis of the improved algorithm,a hardware accelerator for LZMA was designed with FPGA( field programmable gate array) implementation. The hardware accelerator is composed of LZ77 compressor,range encoder and send out controller.Ping-pong operation,parallel matching method with high performance,pipeline processing structure and other acceleration techniques were used to speed up LZMA compression algorithm. While at the same time,data compressed by the circuit is still compatible with standard LZMA file format. The compression rate of the circuit is speeded up to 125 Mb / s,nearly 10 times faster than that of the software based LZMA. The processing relative data of each clock is speeded up nearly 200 times. Results from the experiments on ML605 basing on a Virtex-6 FPGA development kit,show the accelerator is correct and feasible.