FPGA Codesign Implementation of Vector Directional Filter

A Boudabous,A Ben Atitallah,L Khriji,N Masmoudi,P Kadionik

doi:10.1109/ipta.2008.4743773

FPGA Codesign Implementation of Vector Directional Filter

A Boudabous, A Ben Atitallah + Show 3 more

https://doi.org/10.1109/ipta.2008.4743773

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Publication Date: Nov 1, 2008

Citations: 10

Affiliation: Sultan Qaboos University, Institut Polytechnique de Bordeaux

#Vector Directional Filter #Use Of Hardware Accelerator + Show 8 more

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Abstract

Recently, Vector Directional Filter (VDF) have been developed either as software based applications or hardware using DSP (digital single processing) technologies. In this paper, we present a new efficient hardware/software (HW/SW) codesign implementation of the VDF using embedded system development board. By means of VHDL language, hardware accelerator including VDF algorithm is implemented with fast pipelined architecture. The remaining parts were realized in software using NIOS II softcore processor and Clinux as operating system. Experimental results confirm that the use of hardware accelerator gives good results concerning image quality and filtering speed.

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