FPGA-Based Permanent Magnet Synchronous Machine Emulator With SiC Power Amplifier

Abstract

Power-hardware-in-the-loop (PHIL) platforms are gaining increasing attention as a valid solution for testing of converters operating in power electronics systems. Complex systems of significant power are difficult to validate experimentally in the laboratory. When, in such contexts, the device under test (DUT) is represented by a power converter designed to supply a variable speed drive (VSD), the electrical machine can be emulated through the PHIL platform. However, emulation of electrical machines imposes several requirements to the design of the PHIL test platform. Indeed, the emulable range of the machine operating points is constrained by the choice of the dc-bus voltage and of the coupling network. Furthermore, coupling network sizing strongly affects the stability of the emulation. In this article, the analytical relation between the coupling network, the emulator dc-bus voltage, and the machine operating range is described. A design procedure is then derived for both the dc-bus voltage and the coupling network. Afterward, the stability analysis is carried out to determine the stability characteristic of the PHIL emulation as a function of the coupling network choice and of the main parameters of the DUT control loop. The FPGA implementation of the PHIL is then described. Simulation and experimental results show the capability of the proposed implementation, with respect to both transient and steady-state machine emulation.