Abstract

Embedding a soft IP core inside an FPGA has many advantages such as customization, design reuse, accelerating the design cycle and narrowing the time to market window thereby enhancing the productivity. In view of all the above mentioned advantages, the FPGA based systems are now penetrating the embedded arena which has marked the take off of the configware rather than the traditional embedded hardware and software. The complexity of the FPGA based SoCs in an Embedded paradigm has now been addressed by the designers by using the configware libraries that comprises of the soft IP cores. The design techniques pertaining to the soft IP cores are now regarded as the evolutionary techniques and the novel design methodologies of the Embedded Systems has comes out to be just an analytical marriage of the above mentioned soft IP cores. Pre-designed and pre-verified soft IP cores such as the ones designed in this chapter addresses the pertinent issues such as time to market, performance, area, power metrics etc. Further designing such soft IP cores in Handel C facilitates maximum flexibility and reconfigurability to match the requirements of a specific embedded design application. All the cores reported in this chapter have been verified/prototypes on the Xilinx Starter kit.

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