FPGA based low power hardware for quality access control of compressed gray scale image

Abstract

This paper proposes novel hardware architecture of passive data-hiding scheme for quality access control of digital image in discrete cosine transform compressed domain. Both serial and parallel hardware implementation are done and a comparative detail model’s performance is reported. Passive data hiding is a technique used for media identification where it is expected that signal distortions caused due to data hiding can be reverted by the authorized user to enjoy the full quality. The main objectives of hardware assisted passive data hiding are to achieve low power usage, reliability, real-time performance, and ease of integration with existing consumer electronic devices. The proposed architecture is synthesized using Xilinx’s ISE for a field-programmable gate array and also tested over large number of benchmark images. It is seen that (a) in real time processing, the scheme saves 90.42% power than the related implementation found in the literature, (b) a very high throughput of 11.37 and 11.41 Mb/s are achieved with parallel implementation for access control encoder and decoder, respectively at a maximum operating frequency of 111.03 MHz for an image of size (512 × 512). Obtained experimental results are also compared with related schemes and found to be superior.