FPGA Based Implementation of Semi-Fragile Watermarking Algorithm

Abstract

This paper presents an FPGA implementation of a semi-fragile watermarking-based algorithm for a digital camera. The architecture of digital authentication camera is discussed and a semi-fragile watermarking algorithm based the invariant property of DCT coefficients quantization is designed which can survive a certain amount of compression. The components of a digital camera and the watermarking algorithm are described in Verilog HDL and implemented on the DE2-70 board. The results shown that the hardware implementation can provide real time performance and resist off-line attacks compare with the software-assisted solution.