FPGA based Implementation of Low power CORDIC architecture

Abstract

The coordinate rotation digital computer (CORDIC) is a shift-add algorithm used for rotating vectors in a plane. Several techniques are proposed in the literature for calculation of trigonometric functions which requires large memory usage. Due to the flexibility, CORDIC algorithm is best alternative and allows high quantization accuracy by maximizing word length. The linear-rate convergence creates the major problem in CORDIC algorithm with the source of word-length and iteration speed. The power consumption is also a major issues which affects the performance due to array of shift-add operations. For further improvement, in this paper, we propose a low power and high speed CORDIC design with an improved power control and hardware reduction techniques. We employ the canonical signed-digit (CSD) technique and Hcub algorithm for reducing the number of shifters and adder/subtractor in the design. Then, we proposed an adder based on the advanced Boolean logic technique. These three techniques are used to redesign the entire CORDIC logic stages in [16] thereby contributing in power consumption reduction. The functionality of proposed CORDIC algorithm is assessed through FPGA implementations. The simulation result shows that the proposed method has higher frequency of 78.91 %, 83.42%, 79.89% and 77.01 % when compared with other architectures.