FPGA Based Implementation of Linear SVM for Facial Expression Classification

Abstract

This work presents a Field Programmable Gate Array (FPGA) based hardware efficient implementation of One-Versus-All (OVA) multi-class linear Support Vector Machine (SVM) classifier for classifying the facial expressions of an individual. The aim is to achieve a real-time classification of the facial expressions into three different states viz., neutral, happy, and pain. The target is to make the designed architecture feasible for an embedded platform based FER system so that it could assist in monitoring patients in hospitals. Thus, in the context of architectural design, the challenge here is to achieve classification accuracy equivalent to the software-based implementation with a multi-fold improvement in the execution speed. The acceleration in the execution speed of the designed classifier is achieved utilizing the parallelism and the pipelining concepts of the VLSI architecture design. Moreover, to reduce the computational cost and to further boost the execution speed of the architecture, we have adopted the fixed-point data format (Q24.16) in our design. We have trained the classifier offline and then used the designed architecture with learned parameters to perform testing on the hardware. The designed architecture after synthesis operates at a maximum clock frequency of 241.55 MHz on Xilinx ML510 FPGA platform. Classification accuracy of 98.50% equivalent to its software counterpart has been achieved on simulating the designed architecture with different test images. Thus, the designed classifier architecture achieved good performance in terms of speed, area, and accuracy, and is thus, a favorable candidate for real-time classification of the facial expressions on an embedded platform based on FPGA.