Abstract
Fully homomorphic encryption (FHE) allows arbitrary computation on encrypted data and has great potential in privacy-preserving cloud computing and securely outsource computational tasks. However, the excessive computation complexity is the key limitation that restricting the practical application of FHE. In this paper we proposed a FPGA-based high parallelism architecture to accelerate the FHE schemes based on the ring learning with errors (RLWE) problem, specifically, we presented a fast implementation of leveled fully homomorphic encryption scheme BGV. In order to reduce the computation latency and improve the performance, we applied both circuit-level and block-level pipeline strategies to improve clock frequency, and as a result, enhance the processing speed of polynomial multipliers and homomorphic evaluation functions. At the same time, multiple polynomial multipliers and modular reduction units were deployed in parallel to further improve the hardware performance. Finally, we implemented and tested our architecture on a Virtex UltraScale FPGA platform. Runing at 150MHz, our implementation achieved $4.60\times \sim 9.49\times $ speedup with respect to the optimized software implementation on Intel i7 processor running at 3.1GHz for homomorphic encryption and decryption, and the throughput was increased by $1.03\times \sim 4.64\times $ compared to the hardware implementation of BGV. While compared to the hardware implementation of FV, the throughput of our accelerator also achieved $5.05\times $ and $167.3\times $ speedup for homomorphic addition and homomorphic multiplication operation respectively.
Highlights
The fully homomorphic encryption (FHE) [1] provides a theoretical and practical solution for cloud computing security and privacy-preserving, which can directly perform the arbitrary computations over ciphertext without disclosing the personal sensitive information
We present a complete FPGA-based hardware accelerator for homomorphic encryption and homomorphic evaluation of BGV leveled FHE scheme, which is the first efficient FHE scheme based on Learning with Error (LWE) or Ring LWE (RLWE) problem, and it is an important basis for other FHE variant algorithms
RESOURCE CONSUMPTION The proposed hardware accelerator for Ring-LWE based BGV scheme is descripted with Verilog HDL language, synthesized and implemented in Xilinx VIVADO on a Virtex UltraScale FPGA platform, which has a chip XCVU125FLVA2014-1HV-E
Summary
The fully homomorphic encryption (FHE) [1] provides a theoretical and practical solution for cloud computing security and privacy-preserving, which can directly perform the arbitrary computations over ciphertext without disclosing the personal sensitive information. The associate editor coordinating the review of this manuscript and approving it for publication was Yiming Huo. FHE has the property that any computation on ciphertext is equivalent to performing the same computation on plaintext, the users can obtain the final result by decrypting the ciphertext with private keys. RELATED WORK As mentioned above, software implementations are not yet efficient enough for real-time applications, which may require minutes or hours to evaluate some simple functions or algorithms. A homomorphic evaluation of AES-128 [16] is reported to take over 36 hours based on the NTL C++ library, and running on a Intel Xeon processor with 2.0GHz and 256GB RAM. Even using SIMD techniques, the amortized rate is about 40 minutes per block Another software homomorphic evaluation of the decryption function of a lightweight block cipher SIMON-32/64
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