FPGA - based evaluation of power analysis attacks and its countermeasures on Asynchronous S-Box

Abstract

A novel asynchronous S-Box design for AES cryptosystems is proposed and validated. The S-Box is considered as the most critical component in AES crypto-circuits since it consumes the most power and leaks the most information against side channel attacks. The proposed design completely based on a delay insensitive logic paradigm known as Null Conversion Logic (NCL). Asynchronous S-Box is based on self-time logic referred to as NCL which supports few beneficial properties for resisting SCAs such as clock free, duail rail encoding and monotonic transitions so that it consumes less power therefore suitable for energy constrained mobile crypto-applications. These beneficial properties make it difficult for an attacker to decipher secret key embedded within the cryptographic circuits of the FPGA board. Resistant to SCAs of both existing and proposed S-Box design are presented using differential power analysis (DPA) and correlation power analysis (CPA) attacks. The power measurement result showed that the NCL S-Box had lower total power consumption than original and effective against DPA and CPA attacks.