FPGA-based Design of Multiple Models for Industry 4.0 Cyber Security

Abstract

Industry 4.0 computing infrastructure depends on traditional processing platforms, and all these platforms perform well and achieving acceptable throughput. Two significant problems confront with these platforms are the delay in data processing and security hazard for potential threats. A design coding has been written using VHDL based on behaviour temporal parallelism for Industry 4.0 cybersecurity model. The models are divided into three namely, single, dual and quad models. Every model has three main components include UART, FIFO and DES algorithm for data encryption and decryption. Encryption is achieved more than one block at a time and over the number of designs to find the most suitable application for data processing. A DES algorithm based efficient implementing the design of 16-round multiple parallel models for low-cost, scalable, and robust encryption solution of a maximum clock frequency of 227MHz and it is capable of encrypting or decrypting data blocks at a rate of throughput 58,288Mbps.