FPGA-Based Architecture for a Generalized Parallel 2-D MRI Filtering Algorithm

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doi:10.3844/ajeassp.2011.566.575

Abstract

Problem statement: Current Neuroimaging developments, in biological research and diagnostics, demand an edge-defined and noise-free MRI scans. Thus, this study presents a generalized parallel 2-D MRI filtering algorithm with their FPGA-based implementation in a single unified architecture. The parallel 2-D MRI filtering algorithms are Edge, Sobel X, Sobel Y, Sobel X-Y, Blur, Smooth, Sharpen, Gaussian and Beta (HYB). Then, the nine MRI image filtering algorithm, has empirically improved to generate enhanced MRI scans filtering results without significantly affecting the developed performance indices of high throughput and low power consumption at maximum operating frequency. Approach: The parallel 2-d MRI filtering algorithms are developed and FPGA implemented using Xilinx System Generator tool within the ISE 12.3 development suite. Two unified architectures are behaviorally developed, depending on the abstraction level of implementation. For performance indices comparison, two Virtex-6 FPGA boards, namely, xc6vlX240Tl-1lff1759 and xc6vlX130Tl-1lff1156 are behaviorally targeted. Results: The improved parallel 2-D filtering algorithms enhanced the filtered MRI scans to be edge-defined and noise free grayscale imaging. The single architecture is efficiently prototyped to achieve: high filtering performance of (11230 frames/second) throughput for 64*64 MRI grayscale scan, minimum power consumption of 0.86 Watt with a junction temperature of 52°C and a maximum frequency of up to (230 MHz). Conclusion: The improved parallel MRI filtering algorithms which are developed as a single unified architecture provide visibility enhancement within the filtered MRI scan to aid the physician in detecting brain diseases, e.g., trauma or intracranial haemorrhage. The high filtering throughput is feasibly nominee the nine parallel MRI filtering algorithms for applications such as real-time MRI potential future applications. Future Work: a set of parallel 3-D fMRI filtering algorithms will be investigated to be developed and fast FPGA prototyped for future research project.

Highlights

FPGAs are increasingly used in modern parallel Filtering algorithm applications such as medical imaging (Leeser et al, 2005), Mapping distributed implemented utilizing hard IPs (DSPs) Algorithms (Maslennikow and Sergiyenko, 2006), image processing (Kiran, 2008), power consumption in portable image processing (Atabany, 2008), MPEG-4 motion estimation in mobile applications (Gao, 2003), satellite data processing (Nataraj et al, 2009), new Mersenne Number Transform (Nibouche et al, 2009), high speed wavelet-based image compression (Masoudnia et al, 2005) and even the global communication link (Mak et al, 2008)
One of the challenging goals of this study is not appear in the architecture’s circuit. These signals developing an efficient FPGA implementation that are internally generated when the FPGA provides fast FPGA prototyping for high filtering implementation is behaviourally compiled within performance of the nine parallel 2-D magnetic resonance imaging (MRI) filtering
The Xilinx Timing Analyzer by more than one performance efficient architecture, is utilized to generate time statistics, total power analysis depending on the abstraction level of implementation. and histogram charts of FPGA implementation paths

Summary

INTRODUCTION

FPGAs are increasingly used in modern parallel Filtering algorithm applications such as medical imaging (Leeser et al, 2005), Mapping DSP Algorithms (Maslennikow and Sergiyenko, 2006), image processing (Kiran, 2008), power consumption in portable image processing (Atabany, 2008), MPEG-4 motion estimation in mobile applications (Gao, 2003), satellite data processing (Nataraj et al, 2009), new Mersenne Number Transform (Nibouche et al, 2009), high speed wavelet-based image compression (Masoudnia et al, 2005) and even the global communication link (Mak et al, 2008). The 2-D image filtering purpose of the above nine per-processing algorithms is detecting sharp changes in image brightness by significantly reducing the amount of data to be processed, filtering out information that may be regarded as less relevant, while preserving the important structural properties of an image. The nine different MRI filtering algorithms are streams using convolution filters vector as shown in Fig. efficiently developed, implemented and, improved 1. The in a unified architecture using Xilinx system generator filter architecture, as shown, consists of an tool (Xilinx, 2010) within the ISE 12.3 development image sample stream buffer, filter coefficient memory, suite to target two Virtex-6 FPGA (Virtex-6, 2010) comparator, address control unit, MAC unit and boards, namely, xc6vlX240Tl-1lff1759 and capture register.

Input 2-D Segmentation MRI Stage

AND DISCUSSION

CONCLUSION