FPGA based Adaptive Lock-in Amplifier

Abstract

An adaptive Lock-in Amplifier (LIA), which works for sinusoidal signals in the frequency range of 9 - 11 kHz and an amplitude range of 0.3 - 10 V is being proposed. LIAs can extract useful signals from a very high noisy environment. For an adaptive LIA, the reference signal has to be generated by a phase locked loop (PLL) from the incoming signal. The phase and frequency error between the reference and input signals may reduce the accuracy of LIA system. To eliminate this error, a PLL with an enhanced phase detector is proposed. Using this quadrature PLL (QPLL), the accuracy of the LIA has effectively increased in the designed frequency range. The simulation results show that the proposed model can extract the amplitude of the signal buried in noise with a signal-to-noise ratio (SNR) as small as 10 dB and harmonics. The system-on-chip implementation of the adaptive LIA is carried out in the Altera Stratix III FPGA device. Testing the implementation for noise as well as harmonics have been performed in the designed frequency and amplitude range.