Abstract
The Square Kilometre Array (SKA), currently in the pre-construction phase, will be the world largest telescope array for radio astronomy. The Fourier domain acceleration search (FDAS) is a sub-module of the Non-imaging Processing Pulsar Search Sub-element (NIP PSS) of SKA-MID Central Signal Processor (CSP) element. The total performance needed for FDAS module of up to 2000 beams is over 14Poperations/s. The huge scale of it is a strong computing challenge. In this work, the use of FPGAs to accelerate the FDAS module is studied, due to their high inherent parallelism and power efficiency. We study the impact of the relaxation of a number of FDAS factors and test them using a Terasic DE5 board. By applying all the relaxation methods, up to 93% FPGAs can be saved. Further, several optimization techniques are introduced to reduce the number of needed FPGAs.
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