FPGA and Embedded Systems Based Fast Data Acquisition and Processing for GEM Detectors

Abstract

Gas electron multiplier (GEM) detectors (Sauli in Nucl Instrum Methods Phys Res A 805:2–24, 2016. https://doi.org/10.1016/j.nima.2015.07.060 (special issue in memory of Glenn F. Knoll); Buzulutskov in Instrum Exp Tech 50(3):287–310, 2007. https://doi.org/10.1134/S0020441207030013) are widely used for detection of ionizing radiation. When used in the proportional mode, they provide information about time, location, and energy of a detected particle (Chernyshova et al. in Fusion Eng Design, 2017. https://doi.org/10.1016/j.fusengdes.2017.03.107; Altunbas et al. in Nucl Instrum Methods Phys Res A 490(1–2):177–203, 2002. https://doi.org/10.1016/S0168-9002(02)00910-5. http://linkinghub.elsevier.com/retrieve/pii/S0168900202009105). Modern technologies allow full utilization of detector properties, by acquiring the waveform of output current pulses and processing them using sophisticated digital signal processing (DSP) algorithms. The current pulses must be digitized at high speed (up to 125 MHz) with high resolution (up to 12-bits). Due to the high volume of the produced data, it is necessary to provide the high-performance data acquisition system (DAQ) to transmit the data to processing units. Efficient processing of the GEM data requires distributed parallel processing system to perform multiple tasks (Czarski et al. in Rev Sci Instrum 87(11), 11E336, 2016. https://doi.org/10.1063/1.4961559): (1) Filter out the background and transmit only hit related data. (2) Extract the parameters of a hit, describing the time and charge (related to energy). (3) Estimate the hit position by combining information from multiple anode pads. (4) In case of 2D GEM detectors, correlate pulses received from X and Y pads (pixels) or W, U and V pads (pixels). (5) Separate the hits overlapping in space or in time (if possible) to support detector operation at higher rates. The above functionalities may be achieved in different hardware architectures. The typical hardware platforms include FPGA chips, standard or embedded computer systems with different computation accelerators (Wojenski et al. in J Instrum 11(11):C11035, 2016. http://stacks.iop.org/1748-0221/11/i=11/a=C11035; Nowak et al. in J Phys Conf Ser 513(5):052–024, 2014. https://doi.org/10.1088/1742-6596/513/5/052024. http://stacks.iop.org/1742-6596/513/i=5/a=052024?key=crossref.c5912cfa72c30b309821e14c4384948f. The paper shows possible solutions with their feasibility for particular applications.