FPGA acceleration of a pseudorandom number generator based on chaotic iterations

Abstract

As any well-designed information security application uses a very large quantity of good pseudorandom numbers, inefficient generation of these numbers can be a significant bottleneck in various situations. In previous research works, a technique that applies well-defined discrete iterations, satisfying the reputed Devaney's definition of chaos, has been developed. It has been proven that the generators embedding these chaotic iterations (CIs) produce truly chaotic random numbers. In this new article, these generators based on chaotic iterations are redesigned specifically for Field Programmable Gate Array (FPGA) hardware, leading to an obvious improvement of the generation rate. Analyses illustrate that statistically perfect and chaotic random sequences are produced. Additionally, such generators can also be cryptographically secure. To show the effectiveness of the method, an application in the information hiding domain is finally proposed.