Abstract
This paper describes an on-chip interface for recovering power and providing full-duplex communication over an AC-coupled 4-wire lead between active implantable devices. The target application requires two modules to be implanted in the brain (cortex) and upper chest; connected via a subcutaneous lead. The brain implant consists of multiple identical “optrodes” that facilitate a bidirectional neural interface (electrical recording and optical stimulation), and the chest implant contains the power source (battery) and processor module. The proposed interface is integrated within each optrode ASIC allowing full-duplex and fully-differential communication based on Manchester encoding. The system features a head-to-chest uplink data rate (up to 1.6 Mbps) that is higher than that of the chest-to-head downlink (100 kbps), which is superimposed on a power carrier. On-chip power management provides an unregulated 5-V dc supply with up to 2.5-mA output current for stimulation, and two regulated voltages (3.3 and 3 V) with 60-dB power supply rejection ratio for recording and logic circuits. The 4-wire ASIC has been implemented in a 0.35-n}{}mu text{m} CMOS technology, occup-ying a 1.5-mm2 silicon area, and consumes a quiescent current of n}{}91.2~mu text{A} . The system allows power transmission with measured efficiency of up to 66% from the chest to the brain implant. The downlink and uplink communication are successfully tested in a system with two optrodes and through a 4-wire implantable lead.
Highlights
N EURAL Prostheses have experienced significant progress in the last two decades [1], generating real impact in clinical applications such as cochlear implants and deep brain stimulation (DBS) therapy
The power management and full-duplex communication circuits have been configured and fabricated in two different form factors: (i) as a complete system embedded within the optrode to be used in the end-application, with only access points being connections to the 4-wire lead; and (ii) as a standalone test circuit, with the Clock and Data Recovery (CDR), Phase Locked loop (PLL) and power management unit are accessible for testing purposes
The 4-wire ASIC was tested under various conditions using a 2-channel function generator to provide the power/downlink
Summary
N EURAL Prostheses have experienced significant progress in the last two decades [1], generating real impact in clinical applications such as cochlear implants and deep brain stimulation (DBS) therapy. Basic research and new translational efforts are developing Brain Machine Interfaces (BMIs) and closed loop therapies for epilepsy and Parkinson’s [2]–[4] These advances are in part due to ever improving microtechnology, allowing integrated implantable medical. Generation devices are developing multi-implant active modules [8] that will require intra-body communication and a means of sharing power [9]. This paper is organized as follows: Section II introduces the multiimplant system concept and key requirements; Section III describes the communication channel (4-wire lead); Section IV analyses the power transfer efficiency; Section V details the circuit implementation; Section VI presents the fabricated system; Section VII presents silicon verified measurements and Section VIII concludes this work
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