Four-cycle butterfly arithmetic architecture

Abstract

Digital signal processing (DSP) is one of the fastest growing areas of microcomputer technology. The increasing interest in DSP is not simply due to the introduction of new theories or to the expanding range of DSP applications, but to the availability of high-speed devices that make DSP economically possible. This application note from TRW describes briefly the ubiquitous fast Fourier transform (FFT) and considers the architecture necessary to implement it using high-speed multiplier-accumulators. The proposed FFT processor uses four real multipliers and six real adders to implement a four-cycle butterfly sequence (one of the basic building blocks of the FFT generator). A.C.