Four BIT CMOS full adder in submicron technology with low leakage and Ground bounce noise reduction

Abstract

For the design and analysis of complex arithmetic circuits, Ground bounce noise is given an equal importance in the list of low power performance measuring parameters like leakage current, active power, delay and area. In this paper leakage power and the ground bounce noise is considerably reduced by the use of sleep transistor in full adder design. Size of the sleep transistor is determined by transistor resizing approach. 4 bit adder is implemented using 1 bit adder as reference. The simulation shows that, the 1 bit and 4 bit adders are efficient in terms of standby leakage power, active power and ground bounce noise. Simulations have been performed using T-Spice 90nm and 65nm CMOS technology with supply voltage of 5v and 3.3v at room temperature.