Formula omitted] Parallel paths for non-linearity mitigation in ring oscillator based analog-to-digital conversion

Abstract

A new technique to mitigate the non-linearity of the ring oscillator is introduced and described for open loop ring oscillator based analog-to-digital conversion. The idea is based on limiting the input signal amplitude to make the ring oscillator work in a more linear range, thus improving the SNDRpeak. The dynamic range is preserved by means of several parallel digitization channels injected in phase. Passive interpolation between the channels is exploited to ensure a uniform distribution of the output phases. The idea is validated through system and schematic simulations using a 65 nm CMOS technology node, towards high bandwidth applications such as new communication protocols or Internet-of-Things environments. A SNDR of 63 dB is achieved with four digitization parallel channels with an input signal swing of differential 600 mVpp in a bandwidth of 50 MHz. PVT variations and mismatch effects are checked and no degradation in the final resolution is observed. Therefore, the proposal shows a high robustness without requiring any type of calibration. Additionally it is proven that the architecture consumes less than half of the power consumed by the conventional approach, leading to a higher power efficiency.