Formation of Through-Wafer 3-D Interconnects in Fused Silica Substrates by Electrochemical Discharge Machining

Abstract

In recent years, the usage of glass-based materials as substrate in radio-frequency (RF) micro-electro-mechanical-systems (MEMS) applications has increased. Compared to silicon, glass has a lower substrate loss due to its electrically insulative nature. In order to achieve 3D integration, vertical metal-filled vias, commonly used as through-glass vias (TGV) are required in the glass substrate; however, creating through-holes in non-conductive, brittle glass substrates by conventional methods is a quite challenging task. Electrochemical-discharge machining (ECDM) is being extensively explored to create through-holes in glass substrates. In this article, the simultaneous fabrication of multiple through-holes in the glass substrate using a low-cost ECDM technique is presented. Fabrication of through-glass vias by bottom-up copper electrodeposition is demonstrated for the first time. $3\times 3$ through-hole array in fused silica was fabricated using a customized tool electrode made by wire-electric-discharge machining. The through-holes were filled with electrodeposited copper to form through-glass vias (TGVs). Double-sided redistribution lines were fabricated by through-photoresist electrodeposition. The Young's modulus and hardness of the electrodeposited copper in TGVs were measured to be 73.1 GPa and 1.5 GPa respectively. The average electrical resistance of the kelvin TGV was $310 \mathrm{m}\Omega$ , while the daisy chain resistance was $2.45 \Omega$ .