Formation of High Conductivity WSix Layer and its Characterization as a Gate Electrode

Abstract

A novel integrated clustered electrode for gate electrode application has been developed. This method includes a sequential deposition of in situ phosphorus doped polycrystalline silicon and dichlorosilane‐based tungsten silicide films using a clustered platform without a vacuum break. The dopant atom, phosphorus, in the polycrystalline silicon substrate enhances the reduction of , resulting in the formation of an amorphous layer with a uniform thickness and a lower resistivity of 234 μΩ cm. Upon thermal annealing, the composition of the silicide was converted into with an accompanying thickness increase of the silicide. At the interface of /polycrystalline silicon, no defects due to the thickness change were observed at all, while the grain size and the resistivity of the silicide were measured to be 100–400 nm and about 36 μΩ cm, respectively. As a result of its application to a complementary metal oxide semiconductor device having a 0.25 μm minimum linewidth, the line resistance was three times lower than with the conventional . In addition, characteristics such as the dopant depletion of the gate electrode and the reliability of the gate oxide were superior to those of the conventional . This systematic study has also reviewed the correlation between the silicide's structural properties and device performance.