Formation of deep sub-micron buried channel pMOSFETs with plasma doping

Abstract

Plasma Doping (PLAD) is an alternative to conventional beamline ion implantation for the formation of ultra-shallow p/sup +/-n junctions that has been assessed and researched at Varian for several years. In the PLAD process, the silicon wafer to be implanted is placed directly in a plasma containing the desired dopant ions. The wafer is then pulse-biased to a negative potential to accelerate positive dopant ions toward and into the silicon surface. Most of Varian's work to date has used BF/sub 3/ source gas and wafer biases of /spl sim/0.5 to /spl sim/5 kV to implant boron into 150-mm and 200-mm wafers to form ultra-shallow p/sup +/-n junctions. Formation of the ultra-shallow junction depths that are predicted to be needed for 0.18 /spl mu/m technologies (i.e. 60 nm) has been verified by SIMS measurements. Good within-wafer uniformities and wafer-to-wafer repeatability have also been obtained. Deep sub-half micron buried channel pMOSFETs doped at /spl sim/3.5 kV had excellent threshold voltage roll-offs and off-current leakages, high punchthrough resistances, and very good junction leakage characteristics. These results together with the expected small footprint and low cost-of-ownership of such a system make Plasma Doping an attractive doping technique.