Formal Verification of Time Constrains SysML Internal Block Diagram Using PRISM

Abstract

System Modeling Language (SysML) is a standardized profile of Object Management Group (OMG) and it is used for the purpose of graphical modeling a system engineering application. The embedded system is graphically modeled using an internal block diagram of SysML. For formal verification of graphical model, a methodology is proposed which maps the SysML's internal block diagram to input language of PRISM model checker using CTMC (Continuous Time Markov Chain) model for developing more reliable real-time application. The functionality of the system is graphically modeled using an internal block diagram of SysML that is further translated to input language of PRISM. The user requirements are specified using CSL (Continuous Stochastic Logic) which are further verified against the functionality of the system. The timed and untimed properties are presented and verified against the CTMC model. The timed properties involve continuous time as it is critical in embedded system and its verification is necessary. We demonstrate our methodology by applying it on a case study of liquid fertilizer mixing plant and the methodology presents more accurate results.