Formal verification of sequence controllers

Abstract

Sequence controllers are widely used in the chemical processing industries due to the inherently sequential nature of many process operations. In particular, start-up and shut-down operations in continuous processes and any batch operation require sequence controls to force the time-dependent progression of the operation. One incorrect sequence embedded in a sequence control system can potentially cause severe problems. Therefore, all sequences embedded in a sequence control system need to be checked for consistency with design specifications. A formal verification methodology is developed that can systematically verify the functionality of sequence control systems represented at the logic level. Our approach is based on extensions of the recently developed implicit model checking technology, which is particularly well suited to the verification of large and complex systems. The sequence control system is represented implicitly as a system of Boolean equations, and the sequences to be verified are specified formally with temporal logic. Formal verification then requires the solution of a series of Boolean satisfiability problems, which are solved efficiently as integer programming feasibility problems. The methodology is applied to a simplified sequence control system to illustrate its application during the design of sequence control systems. Finally, the methodology is applied to an existing industrial burner management system.