Abstract
AbstractIn this paper we present a methodology for formal verification of hardware/software co‐designs which are represented in RTL/program codes. Two methodologies are proposed. One is for property checking of the above‐mentioned co‐designs, and the other is for equivalence checking between design specifications written in program codes and above‐mentioned hardware/software co‐designs implementing the specifications. The descriptions are translated into FSMD (finite state machine with datapaths) models and described in RTL. Then, descriptions written in different levels are translated into same level descriptions. They can be verified with existing formal verification tools. We also report experimental results. © 2007 Wiley Periodicals, Inc. Electron Comm Jpn Pt 2, 90(7): 11–19, 2007; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/ecjb.20371
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