Formal verification methodology considerations for network on chips

Abstract

Use of Network on Chips (NoCs) as a flexible communication infrastructure is becoming a norm for designing advanced System on Chips (SoCs). However, their implementation complexity is enormous and use of industry proven functional verification methodologies start showing their limitations. Recent research activities have demonstrated that formal verification is capable of addressing most of the bottlenecks faced by functional verification techniques. In this context, this paper presents a survey on recent advances in the field of Formally verifying a Network on Chip (NoC). An overview of NoC design challenges is presented along with their formal verification methodologies. The paper concludes by highlighting that going forward, a Unified Formal Verification Methodology (UFVM) must be driven to ensure that the benefits of formal verification are reaped.