Formal timing verification techniques for distributed system

Abstract

Formal specification and timing verification of distributed system are important. As concerns formal specification and verification of distributed system, SDL and LOTOS, Estelle have been standardized and studied. But we can nor formally specify and verify timing conditions and fairness by these methods. In this paper, we propose formal timing specification and verification including strong fairness. We have developed CASE tool based on this method. We specify concurrent processes behavior by process algebra and internal sequential behavior by automaton. System specification is automatically generated from both concurrent processes behavior specification and internal sequential behavior specification. We specify verification property specification by timed automaton. Timing verification is realized by language inclusion algorithm and inequality method. We show this method effective by CASE tool.