Formal Modelling and Verification of IEC61499 Function Blocks with Abstract State Machines and SMV - Execution Semantics

Abstract

IEC 61499 Standard for Function Blocks Architecture is an executable component model for distributed embedded control system design that combines block-diagrams and state machines. This paper proposes approach to formal modelling of IEC61499 function block execution semantics for popular model checking environment of SMV using Abstract State Machines. An operational semantics of IEC 61499 application with two-stage synchronous execution model is presented using this framework. This paper first introduces the importance of model checking function block applications in different execution semantics. It highlights the uses of formal verification, such as, verifying portability behavior of component based control applications across different implementation platforms compliant with the IEC 61499 standard. The formal model is applied on an example IEC 61499 application. The paper compares the verification results of this IEC 61499 application with two-stage synchronous execution model and the same application with cyclic execution model presented in the earlier work. With this comparison, we verify the portability of the IEC61499 applications across different platforms.