Abstract
Abstract This paper examines a methodology for hardware verification developed by RSRE (Royal Signals and Radar Establishment) in the context of the SRI International's EHDM (Enhanced Hierarchical Design methodology) specification/verification system. The methodology utilizes a four-level specification hierarchy with the following levels: functional level, finite automata model, block model, and circuit level. The properties of a level are proved as theorems in the level below it. In this paper, this methodology is applied to a N-bit counter/multiplexer circuit and is critically examined. The specifications are written in EHDM's specification language, Extended Special, and the proofs are performed using the EHDM theorem prover. Recommendations are made for improving both the RSRE methodology and the EHDM system.
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