Foldable Fan-Out Wafer Level Packaging

Abstract

The constant drive to further miniaturization and heterogeneous system integration leads to a need for new packaging technologies that also allow large area processing and 3D integration with strong potential for low cost applications. Here, Fan-Out Wafer Level Packaging [FOWLP] is one of the latest packaging trends in microelectronics. For FOWLP known good bare dies are embedded into mold compound forming a reconfigured wafer. A redistribution layer is applied on the reconfigured wafer and routes the die pads to the space around and on the die. After bump formation and package singulation by dicing an SMD compatible package is completed. The technology can be also used for multi-chip packages or System in Package (SiP). 3D integration is typically done by package on package (PoP) stacking where the electrical 3D routing is done by through mold vias or vertical interconnect elements [VIE] and a redistribution layer on both sides of the FOWLP. A Foldable Fan-out Wafer Level Package (FFOWLP) would now allow a single sided planar processing and yield a stacked three dimensional package by folding only. Folding can be implemented by a combination of a flexible redistribution layer and a dicing process that only cuts through the molding compound but leaves the redistribution layer untouched. As foldable redistribution layer e.g. polyimide can be used, a standard for flexible substrates. The feasibility of the proposed technology is demonstrated using a multi-chip package. Dies are mold embedded in wafer size. Subsequently the wiring is done by lamination of a polyimide film over the embedded components. In a process flow similar to conventional PCB manufacturing µvias are drilled to the die pads using a UV laser and metalized by Cu-electroplating. Conductor lines and pads are formed by Cu etching. A solder mask can be applied for pad definition. Finally, the wafer will be diced in two steps. First the bending cuts will be done by dicing only through the molding compound and in a second step package singulation will be carried out. Besides folding for package stacking the technology can be also be used to integrate multi-die packages into free form factor surfaces as bows, curves or defined angles. Upscaling of the technology described above from wafer to panel is also possible and offers low cost solutions and large/long foldable FOWLP stripes in a well-defined package.