Abstract

The trend of chip-packaging in the semiconductor industry is pointing towards 3D integrated circuits and scaling down to attain devices with enhanced efficiency and performance. To overcome the reassimilating challenges, we propose the usage of an electroless plated deposition layer to connect pillar bumps and create high-density interconnections. The substrates and pillar arrangements encompass our microchannel with the height of 50 µm or 25 µm where in between the electrolyte is forced with a superficial velocity of 0.3 to 300 mm s−1 in our experiments. The results are compared to a numerical multi-physics model which simulates idealized plating conditions without any disruptions to characterize and quantify the different flow regimes and undesired side-effects. In the low-velocity regime, hydrogen bubbles cannot be dislodged and remain in the microchannel which is accompanied with the formation of extraneous deposition on the resist surface. The mid-velocity regime shows a good match to the simulation model and is considered as optimal plating condition. The chemical reaction slows down for high velocities.

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