Floorplanning with power supply noise avoidance

Abstract

With today's advanced integrated circuits (ICs) manufacturing technology in the deep submicron (DSM) environment, we can integrate entire electronic systems on a single chip (SoC). However, without careful power supply planning in layout, the design of chips can suffer from mostly signal integrity problems, including IR-drop, /spl Delta/I noise, and IC reliability. Post-route methodologies in solving signal integrity problem have been applied but they cause a long turn-around time, which adds costly delays to time-to-market. In this paper, we study the problem of power supply noise avoidance as early as in the floorplanning stage. We show that the noise avoidance in the power supply planning problem can be formulated as a constrained maximum flow problem and present an efficient yet effective heuristic to handle the problem. Experimental results are encouraging. With a slight increase of total wirelength, we achieve almost no IR-drop requirement violation and a 46.6% improvement in /spl Delta/I noise constraint violation compared with a previous approach.