Floorplanning for thermal consideration: Slicing with low power on field programmable gate array

Abstract

In recent years, semiconductor manufacturers focus mainly on shrinking the size of the transistor in Integrated Circuits (ICs) so as to achieve the proliferation in speed and performance of the system. The RC delay is a negligible factor in the submicron technology when compared to a signal propagation delay, it is treated as a dominant factor which leads to many considerations that concerns the end of device scaling and it has accelerated the exploration for curious solutions beyond the perceived limits of current two Dimension (2D) devices. During the floorplan evaluation, heat aware floorplanning methods usually reflect the peak thermal consideration of wirelength and area. Various thermal prototypes which are used to calculate the temperature effects are used in the estimation of peak temperature in an efficient manner. The floorplanning process involves macro placement, partitioning of design, power planning and output ports placement. Various design parameters such as area, timing, power, slicing and performance are considered during the process of floorplanning. Several methods have been discussed on thermal optimization which includes thermal driven floorplanning, placement and routing in this paper. In this paper, different soft computing techniques and improve the results in all aspects are discussed to reduce the power and area and slicing with graph representations are presented. The floorplanning can be done and placements provide better results in this work when compared to other methods.