Floorplanning and Power/Ground Network Design for A Programmable Vision Chip

Abstract

A programmable vision chip integrates a high-speed image sensor and a vision processor on one single chip. It can be adapted to both traditional CV (computer vision) algorithms and deep learning algorithms efficiently. The chip is compute-intensive and memory-intensive, physical design of the chip encounters challenges. This article will introduce a floorplanning and power planning approach appropriate for this large-scale vision chip, limit the influence of IR drop, and finally compare the performance of this experimental result with state-of-the-art chips.