Floorplan and Power/Ground network co-design using guided incremental floorplanning

Abstract

As technology advances, the voltage (IR) drop in the Power/Ground (P/G) network becomes a serious problem in modern IC design. The P/G network co-design with floorplan can improve the power design quality in the floorplanning stage. But it is still hard to find a feasible packing due to the multiple objectives and various constraints. To speed up the searching process, in this paper, we present a method for floorplan and P/G network co-design based on an efficient P/G network analysis scheme and a guided incremental floorplan algorithm to efficiently reduce the violations of the IR drop with the B*-tree representation. Experimental results based on the MCNC benchmarks show that our algorithm successfully fixes the IR drop violations at the floorplanning stage and the intelligent incremental changes efficiently eliminate illegal solutions while maintaining the floorplanning quality and P/G network.