Abstract
This paper describes details of floating-point square root calculation algorithms using Taylor-series expansion and mantissa region division in the viewpoint of the efficient dedicated hardware design. Taylor-series expansions of the square root are examined at the center points of divided mantissa regions, and based on these, square root calculation hardware design balances among accuracy, numbers of basic floating point arithmetic operations (multiplications and additions/ subtractions) as well as the required look-up table size are clarified quantitatively. These results lead to obtaining the suitable algorithm for floating-point square root calculation, and building its corresponding hardware architecture for the digital processor designer.
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