Floating top gate-induced output enhancement of a-InGaZnO thin film transistors under single gate operations

Abstract

This work compares dual gate and single gate a-InGaZnO thin film transistor devices under single gate operations. In both devices, an abnormal drain current increase in the dual gate structures was observed. The results of structural geometry experiments, Technology Computer-Aided Design, and theoretical calculations matching the experimental results provide evidence for a larger voltage potential distribution located near the top gate even when the top gate is floating. Since an additional voltage is formed near the top gate, a better gate control capability will lead to more inverted carriers. Therefore, these dual gate structures have a larger drain current than does the single gate. Finally, both positive bias stress and negative bias illumination stress in both structures are discussed. The results of positive bias stress have shown good quality of the gate insulator layer and negative bias illumination stress was discussed to confirm the coupled voltage.