Floating point acceleration in massively parallel architectures

Abstract

Two techniques for floating point acceleration in bit-serial SIMD massively parallel computers are presented. The first technique does not require any additional hardware with respect to regular bit serial processor implementation; a reduction in the complexity is achieved by a shifting algorithm which minimizes the number of idle processors at each step. The second technique is based on the addition of a hardware stack to each processor. The paper illustrates both the techniques and discusses their complexity.