Abstract
We present our hybrid InP to SiN TriPleX integration interface with a novel alignment technique and its application to complex photonic integrated circuits. The integration interface comprises vertical alignment stops, which simplify the alignment process and allow for array integration with the same simplicity as for single dies. Horizontal alignment is carried out by utilizing optical backscatter reflectometry to get an active feedback signal without the need to operate the chip. Thus, typical contacting limitations of active flip-chip alignment are overcome. By using this method, we demonstrate the integration of InP DFB lasers with more than 60 mW of optical power coupled to a SiN waveguide with an averaged coupling loss of -2.1 dB. The hybrid integration process is demonstrated for single dies as well as full arrays. We evaluate the feasibility of the assembly process for complex photonic integrated circuits by integrating an InP gain chip to a SiN TriPleX external cavity. The process proves to be well suited and allows monitoring chip quality during assembly. A fully functional hybrid integrated tunable laser is fabricated, which is capable of full C-band tuning with optical output power of up to 60 mW.
Highlights
T O DATE, silicon based photonic platforms, such as silicon on insulator (SOI) or SiN TriPleX, have become mature technologies and are widely commercially available [1]–[4]
We demonstrated our hybrid III-V/SiN flip-chip integration interface together with a novel alignment technique based on optical backscatter reflectometry
We show the integration of DFB lasers to SiN waveguides with high reproducibility with an average coupling loss of −2.1 dB and SiN waveguide coupled optical power exceeding 60 mW
Summary
T O DATE, silicon based photonic platforms, such as silicon on insulator (SOI) or SiN TriPleX, have become mature technologies and are widely commercially available [1]–[4]. One is to integrate III-V epitaxial layers on a wafer level by either direct epitaxial growth or bonding of wafer pieces on a silicon photonics wafer that is further processed in the silicon fab for final fabrication of the hybrid-integrated device [5]–[7] This approach has the advantage of a simple optical alignment based on lithographic accuracy and it allows for a high throughput as it is done on a wafer level. A simpler approach is to mount the III-V and silicon photonics chips on individual carriers and butt couple the chips facets by gluing the chip edges together with index matching glue [10], [11] This method is straight forward and yields good performing devices but the position of the coupling interface is limited to the chip edges which makes it incompatible for integration on wafer scale. We will show that OBR alignment is well suited for hybrid integration of such devices, too, and in addition allows monitoring the quality of the PIC during assembly so that faulty devices can be ruled out prior to the assembly
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